Nov. 2023 - Dec. 2023
Synopsis¶
A single-cycle and pipelined RISC-V CPU, described in SystemVerilog. This was a spring term coursework assignment for Imperial module, `Instruction Set Architecture & Compilers’ (IAC). In this group project, I was responsible for designing modules using SystemVerilog as well as writing testbenches with Verilator in C++.
Skills¶
Below are the skills and experiences gained from the project:
Competencies with C++ and SystemVerilog
Competency using Verilator
Competency using GitHub for collaborative development
Competency using shell scripts
Knowledge of computer architecture theory and principles
Experience working in a team
